Efficient Method for the Error Protection of Cache Memory by using the Similarity of Tag Bits

High performance processors make use of caches to increase the rate at which they can process the data. Soft errors can corrupt the information in the memory especially in cache memory which is the closest data storage to the CPU. Cache tag field are critical to correctness of cache access and to achieve high hit rate. Complex protection mechanism to tag bit information can degrade the performance due to longer cache access latency. Using the spatial locality of memory accesses error protection of tag bits is improved. The error correcting capability of tag bits is enhanced by exploiting the similarity of tag bit values. It is checked if neighbouring cache lines have the same tag bits as that of the data fetched, when data is fetched from main memory. Same tag bit values are stored as additional bits to be used later in the cache. Simulation of the proposed SIM tag approach is done by varying the number of ways in the cache. Results shows that proposed approach improves the error protection capability with negligible performance overheads.